ARPA
Computer Systems and Sofware PI Meeting
San Antonio, Texas
February 14 - 16 1996
Abstract
The recent improvements in parallel compiler technology and packaging technology,
especially MCM technology, have created opportunities for exploration of
new microarchitectures. In the Hydra microarchitecture four high-performance
microprocessors and a merged DRAM-logic second-level cache are integrated
on an MCM substrate. The Hydra microarchitecture represents the first attempt
to design a microarchitecture that is optimized both for executing fine-grained
parallel applications and implementation in MCM technology.
