Kunle Olukotun
Contact Information
Office: Gates Hall 3A, Room 302
Phone: (650) 725-3713
Fax: (650) 725-6949
Email: kunle@ogun.stanford.edu
Address:
- Department of Electrical Engineering
- Stanford University
- Gates Hall 3A, Room 302
- Stanford, CA 94305-9030 USA
Assistant:
- Darlene Hadding
- Administrative Associate for Professor Kunle Olukotun
- Gates 4A-408, M/C 9040
- Phone: (650) 723-1430
- Fax: (650) 725-6949
- darlene@csl.stanford.edu
Office hours:
- Please contact Darlene Hadding for the office hours for the current
quarter.
Research Interests
I am interested in the design, performance analysis and verification
of computers. Currently, I am leading the Hydra single chip
multiprocessor project and the TCC Transactional Coherence and
Consistency project. I am also developing novel simulation, estimation
and verification techniques for system-level design.
Short Bio
Kunle Olukotun is a Professor of Electrical Engineering and Computer
Science at Stanford University and he has been on the faculty since
1991.
Olukotun is well known for leading the Stanford Hydra research project
which developed one of the first chip multiprocessors with support for
thread-level speculation (TLS). Olukotun founded Afara Websystems to
develop high-throughput, low power server systems with chip
multiprocessor technology. Afara was acquired by Sun Microsystems; the
Afara microprocessor technology, called Niagara, is at the center of
Sun's throughput computing initiative. Niagara based systems have
become one of Sun's fastest ramping products ever. Olukotun is actively
involved in research in computer architecture, parallel programming
environments and scalable parallel systems. Olukotun currently co-leads
the Transactional Coherence and Consistency project whose goal is to
make parallel programming accessible to average programmers. Olukotun
also directs the Stanford Pervasive Parallelism Lab (PPL) which seeks
to proliferate the use of parallelism in all application areas.
Olukotun is an ACM Fellow (2006) for contributions to multiprocessors
on a chip and multi threaded processor design. He has authored many
papers on CMP design and parallel software and recently completed a
book on CMP architecture. Olukotun received his Ph.D. in Computer
Engineering from The University of Michigan.
Courses
Current Students
Selected Publications
Chip Multiprocessors (CMPs)
- The Future of
Microprocessors
Kunle Olukotun and Lance Hammond
ACM QUEUE Magazine, September 2005.
- A Single-Chip
Multiprocessor
Lance Hammond, Basem A. Nayfeh and Kunle Olukotun
IEEE Computer Special Issue on "Billion-Transistor Processors",
September 1997.
- The Case for a
Single-Chip Multiprocessor
Kunle Olukotun, Basem A. Nayfeh , Lance Hammond, Ken Wilson and
Kun-Yung Chang
Proceedings of the Seventh International Symposium on
Architectural Support for Parallel Languages and Operating
Systems, October 1996.
Transactional Coherence and Consistency (TCC)
- Tradeoffs in Transactional Memory Virtualizations
JaeWoong Chung, Chi Cao Minh, Austen McDonald, Hassan Chafi, Brian D.
Carlstrom, Travis Skare, Christos Kozyrakis and Kunle Olukotun
To appear in the Proceedings of the Eleventh International Conference
on Architectural Support for Programming Languages and Operating
Systems, San Jose, California, 21-25 October 2006.
-
Architectural Semantics for Practical Transactional Memory
Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh,
Hassan Chafi, Christos Kozyrakis, Kunle Olukotun
Proceedings of the 33rd Annual International Symposium on Computer
Architecture, Boston, Massachusetts, June 17-21, 2006.
-
The Atomos Transactional Programming Language
Brian D. Carlstrom, Austen McDonald, Hassan Chafi, JaeWoong Chung, Chi
Cao Minh, Christos Kozyrakis, Kunle Olukotun
© ACM, (2006). This is the author's version of the work. It is
posted here by permission of ACM for your personal use. Not for
redistribution. The definitive version was published in the
Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language
Design and Implementation, Ottawa, Canada, June 12, 2006.
-
The Software Stack for Transactional Memory: Challenges and
Opportunities
Brian D. Carlstrom, JaeWoong Chung, Christos Kozyrakis, Kunle Olukotun
First Workshop on Software Tools for Multi-Core Systems, Manhattan, New
York, NY, 26 March 2006.
-
The Common Case Transactional Behavior of Multithreaded Programs
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D.
Carlstrom, Christos Kozyrakis, and Kunle Olukotun
12th International Symposium on High Performance Computer Architecture
(HPCA), Austin, Texas, USA, 11-15 February 2006.
-
Transactional Execution of Java Programs
Brian D. Carlstrom, JaeWoong Chung, Hassan Chafi,
Austen McDonald, Chi Cao Minh, Lance Hammond,
Christos Kozyrakis, and Kunle Olukotun
OOPSLA 2005 Workshop on Synchronization and Concurrency in
Object-Oriented Languages (SCOOL), San Diego, California, USA, October
16, 2005.
-
Characterization of TCC on Chip-Multiprocessors
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D.
Carlstrom, Lance Hammond, Christos Kozyrakis, and Kunle Olukotun
The Fourteenth International Conference on
Parallel Architectures and Compilation Techniques,
Saint Louis, Missouri, September 19, 2005.
-
TAPE: A Transactional Application Profiling Environment
Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom,
JaeWoong Chung, Lance Hammond, Christos Kozyrakis, Kunle Olukotun
The 19th ACM International Conference on Supercomputing,
Cambridge, MA, Sunday, June 20, 2005.
-
Transactional Coherence and Consistency: Simplifying Parallel Hardware
and Software
Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael Chen, Christos
Kozyrakis, Kunle Olukotun
Micro's Top Picks,
IEEE Micro November/December 2004 (Vol. 24, No. 6).
-
Programming with Transactional Coherence and Consistency (TCC)
Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben Hertzberg, Mike
Chen,
Christos Kozyrakis, and Kunle Olukotun
Proceedings of the Eleventh International Conference on
Architectural Support for Programming Languages and Operating Systems,
Boston, Massachusetts, October 9-13, 2004.
-
Transactional Memory Coherence and Consistency
Lance Hammond, Vicky Wong, Mike Chen, Ben Hertzberg, Brian D.
Carlstrom,
John D. Davis, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis,
and
Kunle Olukotun
Proceedings of the 31st Annual International Symposium on Computer
Architecture, München, Germany, June 19-23, 2004.
Niagara
-
Maximizing CMP Throughput with Mediocre Cores
John D. Davis, James Laudon., Kunle Olukotun
The Fourteenth International Conference on
Parallel Architectures and Compilation Techniques,
Saint Louis, Missouri, September 19, 2005.
- Niagara: A 32-Way
Multithreaded SPARC Processor
Poonacha Kongetira, Kathirgamar Aingaran, and Kunle Olukotun
IEEE MICRO Magazine, March-April 2005, and presented at Hot Chips 16,
August 2004.
- Article about Kunle Olukuton's Niagara processor: Sun's Big Splash
Linda Geppert
IEEE Spectrum Magazine, January 2005.
Hydra
- Exposing Speculative
Thread Parallelism in SPEC2000
Manohar Prabhu and Kunle Olukotun
Proceedings of the 2005 Principles and Practices of Parallel
Programming, Chicago, IL, June 2005.
- The Jrpm System for
Dynamically Parallelizing Java Programs
Mike Chen and Kunle Olukotun
Special Issue of IEEE Micro: Micro's Top Picks from Computer
Architecture Conferences, Nov./Dec. 2003.
- Using Thread-Level
Speculation to Simplify Manual Parallelization
Manohar Prabhu and Kunle Olukotun
Proceedings of the 2003 Principles and Practices of Parallel
Programming, San Diego, CA, June 2003.
- The Jrpm System for
Dynamically Parallelizing Java Programs
Mike Chen and Kunle Olukotun
Proceedings of the 30th International Symposium on Computer
Architecture, San Diego, CA, June 2003.
- TEST: A Tracer for
Extracting Speculative Threads
Mike Chen and Kunle Olukotun
The 2003 International Symposium on Code Generation and Optimization,
San Francisco, CA, March 2003.
- The Stanford Hydra
CMP
Lance Hammond, Ben Hubbert , Michael Siu, Manohar Prabhu , Mike Chen ,
and Kunle Olukotun
IEEE MICRO Magazine, March-April 2000, and presented at Hot Chips 11,
August 1999.
- Improving the Performance of
Speculatively Parallel Applications on the Hydra CMP
Kunle Olukotun, Lance Hammond, and Mark Willey
Proceedings of the 1999 ACM International Conference on Supercomputing,
Rhodes, Greece, June 1999.
- Exploiting Method-Level
Parallelism in Single-Threaded Java Programs
Mike Chen and Kunle Olukotun
Proceedings of the International Conference on Parallel Architectures
and
Compilation Techniques, Paris, France, October 1998.
- Data Speculation Support
for a Chip Multiprocessor
Lance Hammond, Mark Willey, and Kunle Olukotun
Proceedings of the Eighth ACM Conference on Architectural Support
for Programming Languages and Operating Systems, San Jose, California,
October 1998.
- Considerations in
the Design of Hydra: A Multiprocessor-on-a-Chip
Microarchitecture
Lance Hammond, and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report
CSL-TR-98-749, February 1998.
- A Single Chip
Multiprocessor Integrated with DRAM
Tadaaki Yamauchi, Lance Hammond and Kunle Olukotun
Workshop on Mixing Logic and DRAM preceding the 24th International
Symposium on Computer Architecture, June 1997.
- Software and Hardware for
Exploiting Speculative Parallelism with a Multiprocessor
Jeffery Oplinger, David Heine, Shih-Wei Liao, Basem A. Nayfeh , Monica
Lam and Kunle Olukotun
Stanford University Computer Systems Lab Technical Report
CSL-TR-97-715, February 1997.
- Evaluation of Design
Alternatives for a Multiprocessor Microprocessor
Basem A. Nayfeh , Lance Hammond and Kunle Olukotun
Proceedings of the 23rd International Symposium on Computer
Architecture, May 1996.
- Rationale and Design of the
Hydra Multiprocessor
Note: This is the original MCM based design
Kunle Olukotun, Jules Bergmann, Kun-Yung Chang and Basem A. Nayfeh
Stanford University Computer Systems Lab Technical Report
CSL-TR-94-645, 1994.