A Next Generation Microarchitecture

Stanford Hydra Single-Chip Multiprocessor

Project Overview

Hydra is a new microarchitecture that combines shared-cache multiprocessor architectures, innovative synchronization mechanisms, advanced integrated circuit technology and parallelizing compiler technology to produce breakthroughs in microprocessor cost/performance and parallel processor programmability. In Hydra, four high performance processors are integrated on a single die. Hydra represents a new way to build microprocessors that will demonstrate that it is possible for a multiprocessor to achieve better performance and better cost/performance than wide superscalar mircroarchitecture on sequential applications. Hydra will use a single chip shared cache architecture to fundamentally improve the communication bandwidth and latency between multiple processors. The shared-cache architecture takes advantage of the on-chip bandwidth to provide an order of magnitude improvement in interprocessor communication and synchronization latency compared to current-bus based multiprocessor implementations. This will improve parallel processing efficiency to the point that it is feasible to exploit fine-grained parallelism in sequential programs with a multiprocessor.

The shared-cache architecture and the support for specialized synchronization makes Hydra an ideal target for emerging parallelizing compiler technology. Most of this technology has focused on parallelizing applications into large grains so they will work efficiently on current multiprocessors. With Hydra we will have the ability to exploit fine grained parallelism and so we will develop parallelizing compiler technology that is capable of extracting this sort of parallelism. Using these automatically paralleled applications, we will evaluate Hydra's shared-cache and synchronization mechanisms. This will be the first such evaluation of a shared-cache architecture.

Hydra: A Next Generation Microarchitecture